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PD - 94983
IRF9Z34NPBF
Advanced Process Technology l Dynamic dv/dt Rating l 175C Operating Temperature l Fast Switching l P-Channel l Fully Avalanche Rated l Lead-Free Description
l
HEXFET(R) Power MOSFET
D
VDSS = -55V RDS(on) = 0.10
G S
ID = -19A
Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The TO-220 package is universally preferred for all commercial-industrial applications at power dissipation levels to approximately 50 watts. The low thermal resistance and low package cost of the TO-220 contribute to its wide acceptance throughout the industry.
TO-220AB
Absolute Maximum Ratings
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C V GS EAS IAR EAR dv/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ -10V Continuous Drain Current, VGS @ -10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 screw
Max.
-19 -14 -68 68 0.45 20 180 -10 6.8 -5.0 -55 to + 175 300 (1.6mm from case ) 10 lbfin (1.1Nm)
Units
A W W/C V mJ A mJ V/ns C
Thermal Resistance
Parameter
RJC RCS RJA Junction-to-Case Case-to-Sink, Flat, Greased Surface Junction-to-Ambient
Typ.
0.50
Max.
2.2 62
Units
C/W
02/05/04
IRF9Z34NPBF
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
V(BR)DSS
V(BR)DSS/TJ
RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss
Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. -55 -2.0 4.2
Typ. -0.05 13 55 30 41 4.5 7.5 620 280 140
Max. Units Conditions V VGS = 0V, ID = -250A V/C Reference to 25C, ID = -1mA 0.10 VGS = -10V, ID = -10A -4.0 V VDS = V GS, ID = -250A S VDS = 25V, I D = -10A -25 VDS = -55V, VGS = 0V A -250 VDS = -44V, VGS = 0V, TJ = 150C 100 VGS = 20V nA -100 VGS = -20V 35 ID = -10A 7.9 nC VDS = -44V 16 VGS = -10V, See Fig. 6 and 13 VDD = -28V ID = -10A ns RG = 13 RD = 2.6, See Fig. 10 Between lead, 6mm (0.25in.) nH G from package and center of die contact VGS = 0V pF VDS = -25V = 1.0MHz, See Fig. 5
D
S
Source-Drain Ratings and Characteristics
IS
I SM
VSD trr Q rr ton
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol -19 showing the A G integral reverse -68 p-n junction diode. S -1.6 V TJ = 25C, IS = -10A, VGS = 0V 54 82 ns TJ = 25C, IF = -10A 110 160 nC di/dt = -100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by Starting TJ = 25C, L = 3.6mH
max. junction temperature. ( See fig. 11 )
ISD -10A, di/dt -290A/s, VDD V(BR)DSS,
TJ 175C
RG = 25, IAS = -10A. (See Figure 12)
Pulse width 300s; duty cycle 2%.
IRF9Z34NPBF
100
VGS - 15V - 10V - 8.0V - 7.0V - 6.0V - 5.5V - 5.0V BOTTOM - 4.5V TOP
100
-ID , Drain-to-Source Current (A)
-ID , Drain-to-Source Current (A)
VGS - 15V - 10V - 8.0V - 7.0V - 6.0V - 5.5V - 5.0V BOTTOM - 4.5V TOP
10
10
-4.5V 20s PULSE WIDTH TC = 175C
1 10
-4.5V
1 0.1 1
20s PULSE WIDTH Tc = 25C A
10 100
1 0.1
100
A
-VDS , Drain-to-Source Voltage (V)
-V , Drain-to-Source Voltage (V) DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
2.0
R DS(on) , Drain-to-Source On Resistance (Normalized)
I D = -17A
-ID , Drain-to-Source Current (A)
1.5
TJ = 25C TJ = 175C
10
1.0
0.5
1 4 5 6 7
VDS = -25V 20s PULSE WIDTH
8 9 10
A
0.0 -60 -40 -20 0 20 40 60
VGS = -10V
80 100 120 140 160 180
A
-VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
IRF9Z34NPBF
1200
-VGS , Gate-to-Source Voltage (V)
1000
V GS = 0V, f = 1MHz C iss = Cgs + C gd , Cds SHORTED C rss = C gd C oss = C ds + C gd
20
I D = -10A VDS = -44V VDS = -28V
16
C, Capacitance (pF)
800
Ciss Coss
12
600
8
400
Crss
200
4
0 1 10 100
A
0 0 10 20
FOR TEST CIRCUIT SEE FIGURE 13
30 40
A
-VDS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
100
1000
-ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED BY RDS(on)
10
-I D , Drain Current (A)
100 10s
TJ = 175C TJ = 25C
1
100s 10 1ms
0.1 0.2 0.4 0.6 0.8 1.0 1.2
VGS = 0V
1.4
A
1.6
1 1
TC = 25C TJ = 175C Single Pulse
10
10ms 100
A
-VSD , Source-to-Drain Voltage (V)
-VDS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
IRF9Z34NPBF
20
V DS VGS
RD
ID , Drain Current (A)
-10V
10
Pulse Width 1 s Duty Factor 0.1 %
Fig 10a. Switching Time Test Circuit
5
td(on) tr t d(off) tf
VGS
0
10%
25
50
75
100
125
150
175
TC , Case Temperature ( C)
90% VDS
Fig 9. Maximum Drain Current Vs. Case Temperature
Fig 10b. Switching Time Waveforms
10
Thermal Response (Z thJC )
1
D = 0.50 0.20 0.10 0.05 PDM SINGLE PULSE (THERMAL RESPONSE) t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1
0.1
0.02 0.01
0.01 0.00001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
+
-
15
RG
D.U.T. VDD
IRF9Z34NPBF
E AS , Single Pulse Avalanche Energy (mJ)
VDS
L
500
TOP
400
RG
D.U.T
IAS
-20V
DRIVER
0.01
VDD A
BOTTOM
ID -4.2A -7.2A -10A
tp
300
200
15V
Fig 12a. Unclamped Inductive Test Circuit
100
0 25 50 75 100 125 150
A
175
I AS
Starting TJ , Junction Temperature (C)
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
tp V(BR)DSS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
QG
50K 12V .2F .3F
VG
VGS
-3mA
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
+
QGS
QGD
D.U.T.
-
-10V
VDS
IRF9Z34NPBF
Peak Diode Recovery dv/dt Test Circuit
D.U.T*
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG VGS * dv/dt controlled by RG * ISD controlled by Duty Factor "D" * D.U.T. - Device Under Test
+ V DD
*
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive P.W. Period D=
P.W. Period
[VGS=10V ] ***
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
[VDD]
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
[ISD ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices Fig 14. For P-Channel HEXFETS
IRF9Z34NPBF
TO-220AB Package Outline
2.87 (.113) 2.62 (.103) 10.54 (.415) 10.29 (.405) 3.78 (.149) 3.54 (.139) -A6.47 (.255) 6.10 (.240)
Dimensions are shown in millimeters (inches)
-B4.69 (.185) 4.20 (.165) 1.32 (.052) 1.22 (.048)
4 15.24 (.600) 14.84 (.584)
1.15 (.045) MIN 1 2 3
LEAD ASSIGNMENTS IGBTs, CoPACK 1 - GATE 21- GATE DRAIN 1- GATE 32- DRAINSOURCE 2- COLLECTOR 3- SOURCE 3- EMITTER 4 - DRAIN
LEAD ASSIGNMENTS
HEXFET
14.09 (.555) 13.47 (.530)
4- DRAIN
4.06 (.160) 3.55 (.140)
4- COLLECTOR
3X 3X 1.40 (.055) 1.15 (.045)
0.93 (.037) 0.69 (.027) M BAM
3X
0.55 (.022) 0.46 (.018)
0.36 (.014)
2.54 (.100) 2X NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH
2.92 (.115) 2.64 (.104)
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
E XAMPL E : T HIS IS AN IR F 1010 LOT CODE 1789 AS S E MB L E D ON WW 19, 1997 IN T H E AS S E MB L Y LINE "C" INT E R NAT IONAL R E CT IF IE R L OGO AS S E MB L Y L OT CODE PAR T NU MB E R
Note: "P" in assembly line position indicates "Lead-Free"
DAT E CODE YE AR 7 = 1997 WE E K 19 L INE C
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.02/04
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/

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